1. Field of Invention
The present invention generally relates to a flash memory apparatus, and more particularly to a flash memory apparatus with reference word lines.
2. Description of Prior Art
Please refer to FIG. 1, FIG. 1 is a circuit of a prior art flash memory apparatus 100. The flash memory apparatus 100 includes a reference line control circuit 110, a X decoder 120, a plurality of memory cells M11-Mm3, and a plurality of reference cells R11-Rm3. The X decoder 120 coupled to the memory cells M11-Mm3 and the reference cells R11-Rm3. The X decoder 120 generates and provides the word lines signals W1-Wm to the memory cells M11-Mm3 and the reference cells R11-Rm3, respectively. The memory cells M11-Mm1, M12-Mm2 and M13-Mm3 coupled to bit lines B1, B2 are B3 respectively, and the reference cells R11-Rm1, R12-Rm2 and R13-Rm3 coupled to the reference bit lines R1, R2 and R3 respectively. The reference line control circuit 110 coupled to the reference cells R11-Rm3 and sources of the reference cells R11-Rm3 are grounded or floated by the reference line control circuit 110. The flash memory apparatus 100 compares the currents from one of the bit lines B1-B3 and one of reference bit lines R1-R3 to generate a data output of the flash memory apparatus 100.